It is tempting to drop one ESD array across a USB-C connector and move on. That works on a 480 Mbps phone cable. It does not work once the port runs USB 3.2 Gen 2x2 or USB4 at 10–20 Gbps, because the thing that protects the pin is the same thing that kills the signal: junction capacitance. The right approach is to look at a Type-C connector as up to four separate problems and solve each on its own terms.
On SuperSpeed, capacitance is the whole game
A 10 Gbps lane has a bit period of 100 ps. Hang a few picofarads off that line and you round the edges, close the eye, and fail compliance — long before you ever see an ESD strike. So for the TX/RX pairs the only specs that matter first are capacitance and channel count; everything else is secondary. Aim for 0.2 pF or below per line. These Magnias parts are built for exactly that:
| Part | CJ typ | VRWM | Channels | ESD (contact) | Package |
|---|---|---|---|---|---|
| PT0502N-F2 | 0.2 pF | 5 V | 1 | ±22 kV | DFN0603-2L |
| PS0502Y-F2 | 0.15 pF | 5.5 V | 1 | ±15 kV | DFN0603-2L |
| PZ0502Y-F2 | 0.2 pF | 5 V | 1 | ±20 kV | DFN0603-2L |
| PT0501F-C3 | 0.13 pF | 5 V | 3 | ±8 kV | CSP0603-3L |
Single-line parts let you place protection right at each pin with the shortest possible stub, which matters as much as the diode itself — a low-cap device on a long branch still rings. Where board area is tight, the 3-channel PT0501F-C3 in a 0603 CSP covers a differential pair plus a spare line without spreading capacitance across them.
CC, SBU, and USB 2.0: protect without overthinking
The configuration channel (CC1/CC2) carries the Power Delivery handshake at tens of kHz, the sideband (SBU) is slow, and the legacy D+/D- pair tops out at 480 Mbps. None of them care about a picofarad. Here you can spend that capacitance budget on integration — a single multi-channel array protects several of these lines at once and shrinks the BOM:
- PT0507B-F10 — 4-channel, ~0.7 pF per line, good for CC1/CC2 + SBU1/SBU2 in one part.
- PT0508T-S4 — 2-channel in SOT-143, a tidy fit for the USB 2.0 D+/D- pair.
VBUS is a power pin, not a data line
The most common USB-C protection mistake is treating VBUS like another signal. With Power Delivery, VBUS is no longer 5 V — it negotiates up to 20 V, and Extended Power Range goes to 48 V. A 5 V signal ESD diode on that rail will conduct the moment PD raises the voltage. VBUS needs a TVS whose working voltage sits above the maximum negotiated level: roughly VRWM ≥ 24 V for a 20 V PD port, higher for EPR. Size it for surge current, not capacitance.
The number to design to
Consumer ports are qualified to IEC 61000-4-2: ±8 kV contact and ±15 kV air discharge. Treat ±8 kV contact as the floor, not the target — the parts above clear it with margin (±12 kV to ±22 kV), which buys you headroom for a worn connector, a dry winter, and a few thousand insertions of real-world abuse.