OSFP Optical Module Support ICs

Voltage conversion, power switching, and supervision ICs for 400G, 800G, and 1.6T OSFP transceivers.

OSFP (Octal Small Form-factor Pluggable) is the dominant pluggable optical module form factor for AI-cluster and hyperscale switch interconnect. Each module needs a small but precise set of support ICs — multi-voltage conversion, hot-plug load switching, rail supervision, and signal level shifting — that sit alongside the optical engine and DSP. Magnias provides a complete BOM of LDOs, buck converters, load switches, comparators, and logic for the support circuit, scaling cleanly from 400G to 1.6T module power budgets. The same BOM also supports Linear Pluggable Optics (LPO/LRO) variants, which remove the DSP and can cut module power by up to 40–50% depending on architecture — only the core-supply current ratings change.

400G 800G 1.6T
OSFP optical transceiver module with fiber connector
OSFP pluggable optical module — Magnias supplies the LDO, buck, load switch, supervisor, and buffer ICs that power and sequence the DSP and optical engine inside.

What an OSFP module needs from its support circuit

Each line below names a system-level need and the IC class that addresses it. The same set scales from 400G to 1.6T — only the current ratings change.

System-level need IC class that addresses it
Multi-voltage DC conversion LDO + Buck
Low-IQ analog bias rails Low-quiescent-current LDO
Sub-1 V efficient core supply Buck with BIAS pin
Hot-plug inrush limiting Load switch (controlled slew)
Independent rail sequencing Two load switches
Output discharge on shutdown Load switch with RPD
Voltage supervision / POR Dual comparator
Wire-OR interrupt drive Open-drain buffer
3.3 V → 1.8 V signal bridge (CMIS 5.x two-wire management bus) Level-shifter buffer (push-pull)

Three circuit groups inside every OSFP module

The Magnias OSFP BOM splits into three functional groups. Each group has one or more positioned Magnias parts and a benchmark from a competitor for comparison.

Group 1
Voltage Conversion

Three Magnias parts cover the OSFP voltage tree — fixed photodiode-bias LDO, low-IQ analog bias LDO, and a high-efficiency buck for sub-1V core rails.

PR9030-2V5TF11PSR9031-3V3TF11MI2262G-F15
Group 2
Power Switching & Supervision

Magnias load switches gate the 3.3V rails, a dual comparator monitors rail validity for the host, and an open-drain buffer drives the wire-OR interrupt line.

PSW1510-A10MVC1362-ACML74LVC2G07-TW
Group 3 · Coming Soon
Voltage Domain Crossing

Push-pull level-shifter buffers (2-channel and 3-channel) translate the 3.3V host CMOS signals — including the CMIS 5.x two-wire management bus to the internal MCU — into the 1.8V chipset domain. Magnias roadmap — P/Ns to be supplied.

Coming Soon · roadmap

OSFP support-circuit block diagram

Choose a data rate to see the support circuit. The topology is shared across 400G / 800G / 1.6T — only the current ratings differ. Click (or tap) any green block for the recommended Magnias part. Note: rail names (PD2V5, S4V, DVDDM1, 3V3_1, 3V3_2) are representative — actual labels vary by DSP / TIA / driver vendor.

Block diagram

1.6T OSFP targets next-gen AI cluster interconnect. The support circuit retains the same blocks but with the highest current ratings — the buck's 2A rating on MI2262G-F15 and the load switch's 10A continuous rating on PSW1510-A10 are key headroom margins for this segment. Note: today's 1.6T pluggable OSFP modules (8 × 200G lanes, same cage as 800G) typically operate at ~20–25 W. OSFP-XD is a separate, non-backward-compatible 16-lane form factor that extends the thermal envelope up to ~30 W.

Tap any Magnias-coverage block (green) to see the recommended part. Amber blocks are on the Magnias roadmap.
OSFP_VCC 3.3V
Power input from OSFP host edge connector
T5V5 5.5V
Boosted analog supply rail
LDO · 2.5V Bias
5.5V → 2.5V on rail PD2V5 (photodiode bias)
Analog Bias LDO · 4V
5.5V → 4V on rail S4V (analog driver bias)
Synchronous Buck · 0.72V DSP Core
3 V (rail 3V_DCDC1) → 0.72 V on rail DVDDM1 (~4:1 step-down)
Load Switch · 3V3_1
Hot-plug inrush limit · MCU & SIP rail
Load Switch · 3V3_2
Independent rail sequencing · second instance
Dual Comparator · POR
Monitors rails 3V3_1 / OSFP_VCC · LPWn / RSTn to host
Open-Drain Buffer · INT line
Wire-OR interrupt drive · shared host line
Level Shifter · Coming Soon
3.3V host CMOS → 1.8V chipset · CMIS / I2C bus (push-pull · 2-ch / 3-ch on roadmap)
DSP + Optical Engine
PAM4 DSP, retimer, TIA / driver, lasers
Host MCU + SIP
OSFP MSA management — I2C / two-wire
OSFP Edge Connector
Host-side electrical interface

Magnias parts vs benchmark — side-by-side

Each row compares the Magnias-positioned part to a competitor benchmark on key parameters. The Magnias edge column highlights where the Magnias part wins.

Why Magnias Across the OSFP support BOM, Magnias targets three things: lowest quiescent current on the analog rails, smallest CSP / AQFN footprint at the rail-monitor stage, and FB-set drop-in compatibility on the sub-1 V core rail.

Group 1 · Voltage Conversion

5.5 V → 2.5 V LDO
PR9030-2V5TF11
Parameter Magnias Competitor
V_IN 2.5 – 6 V 1.4 – 5.5 V
V_OUT 2.5 V fixed 2.5 V fixed
I_OUT max 300 mA 150 mA
I_Q 500 nA 50 µA
Dropout 500 mV / 300 mA 230 mV / 150 mA
PSRR @ 1 kHz 60 dB 65 dB
Package TDFN1010-4L SON-6
Magnias edge 100× lower quiescent current, 2× output current, smaller package, comparable PSRR (within 5 dB of competitor at 1 kHz).
Analog Bias LDO · 5.5 V → 3.3 V (adj 4 V via PSR9031-ADS5)
PSR9031-3V3TF11
Parameter Magnias Competitor
V_IN 1.2 – 5.5 V 1.6 – 6.0 V
V_OUT 3.3 V fixed (4 V via -ADS5) 4.0 V
I_OUT max 350 mA 300 mA
I_Q 1.3 µA 6.5 µA
PSRR @ 1 kHz 80 dB 95 dB
Magnias edge 5× lower quiescent current at the analog bias rail. Use the fixed PSR9031-3V3TF11 for the 3.3V rails; the adjustable PSR9031-ADS5 covers the 4 V S4V rail directly when the competitor's fixed 4 V part is the target.
3 V → 0.72 V Synchronous Buck
MI2262G-F15
Parameter Magnias Competitor
V_IN 2.55 – 6 V ≥ 3 V
V_OUT 0.6 – 6 V adjustable 0.72 V FB-set
V_REF 0.6 V ± 1% ≈ 0.5 V
I_OUT max 2 A ~1 A
f_SW 1.6 MHz —
Efficiency Up to 95% —
Package DFN1510-6L WCSP
Magnias edge 2× output current, FB-set drop-in for the 0.72 V DSP core rail.

Group 2 · Power Switching & Supervision

Hot-Plug Load Switch (10A class)
PSW1510-A10
Parameter Magnias Competitor
V_IN 0.1 – 5.5 V 0.5 – 13.5 V
I_OUT continuous 10 A 10.5 A
R_ON typ 4 mΩ 12.8 mΩ
Soft-start Programmable slew Fixed
Discharge Integrated Integrated
Package AQFN 1.5 × 2.0 mm DFN-8 5 × 5 mm
Magnias edge 3× lower R_ON than benchmark (4 mΩ vs 12.8 mΩ) — meaningful at 10A continuous (less heat, smaller thermal margin). 88% smaller package footprint (3 mm² vs 25 mm²) frees board area for the optical engine. Programmable slew rate gives finer control of inrush than fixed-rate competitors. For lighter rails (< 3A) where AQFN is overkill, swap to PSW5192D-C11 (CSP1010-4L).
Dual Voltage Supervisor
MVC1362-AC
Parameter Magnias Competitor
Supply 1.2 – 5.5 V 1.6 – 6.5 V
Output Push-pull Push-pull
Channels 2 (dual) 2 (dual)
Input CM Rail-to-rail Rail-to-rail
t_pd 300 ns @ 100 mV 3 µs typ
Hysteresis Built-in Built-in
Package AQFN 1.5 × 1.5 mm SC-70-8
Magnias edge 10× faster propagation, smaller AQFN package.
Wire-OR Interrupt Buffer
ML74LVC2G07-TW
Parameter Magnias Competitor
V_CC 1.65 – 5.5 V 1.65 – 5.5 V
V_I tolerance 0 – 5.5 V 0 – 5.5 V
V_O off 0 – 5.5 V 0 – 5.5 V
I_OL drive 24 mA 24 mA
t_pd max 3.7 ns ~5 ns
Channels 2 (use 1) 1
Magnias edge Faster, dual-channel flexibility for future expansion.

Group 3 · Voltage Domain Crossing (Roadmap)

Push-pull level-shifter buffers — 2-channel and 3-channel variants for the 3.3 V → 1.8 V CMIS / I2C management bus into the chipset domain. Target specs: rail-to-rail any-V_CC tolerance, < 5 ns t_pd, sub-µA I_CC, DSBGA-class footprint. Magnias roadmap — P/Ns and sample timing on request.

Magnias OSFP BOM summary

Function Magnias P/N Package Applies to Notes
5.5V → 2.5V LDO (photodiode bias) PR9030-2V5TF11 TDFN1010-4L All rates · rail PD2V5 300 mA, 500 nA IQ. 100× lower IQ than competitor benchmark.
Analog Bias LDO (5.5V → 3.3V; 4V via -ADS5) PSR9031-3V3TF11 TDFN1010-4L All rates · analog bias rails (incl. S4V via adjustable variant) 350 mA, 1.3 µA IQ — 5× lower than competitor. Use PSR9031-3V3TF11 fixed for 3.3 V analog rails; use PSR9031-ADS5 adjustable to hit the 4 V S4V driver-bias rail.
3V → 0.72V Synchronous Buck MI2262G-F15 DFN1510-6L All rates · DSP core rail DVDDM1 2 A, 1.6 MHz, up to 95% efficient. Drop-in for FB-set 0.72V.
3V3 Hot-Plug Load Switch (main, 10A class) PSW1510-A10 AQFN 1.5×2.0 mm-10L All rates · two instances (3V3_1 / 3V3_2) 10 A continuous, 4 mΩ R_ON typ (6 mΩ max). Wide VIN 0.1–5.5V. Programmable slew rate + integrated discharge.
3V3 Hot-Plug Load Switch (alt) PSW5192D-C11 DFN All rates · same position Alternative load switch with 65 Ω discharge and verified soft-start.
Dual Comparator / Supervisor MVC1362-AC AQFN 1.5 × 1.5 mm All rates · LPWn / RSTn (OSFP MSA) 300 ns t_pd, push-pull, rail-to-rail. 10× faster than competitor.
Open-Drain Buffer (wire-OR) ML74LVC2G07-TW SOT-563 All rates · INT line (OSFP MSA) Dual-channel, 24 mA I_OL, 5.5V tolerant. 3.7 ns t_pd max.
Level Shifter 2-ch / 3-ch (push-pull) Coming Soon — All rates · 3.3V → 1.8V CMIS / I2C bus bridge Magnias roadmap — P/Ns to be supplied. Contact Magnias FAE for sample timing.

Request samples or an OSFP design review

Designing a 400G, 800G, or 1.6T OSFP module? Need samples of the LDO / buck / load-switch / comparator parts above, or want our FAE team to review the support-circuit BOM against your DSP and optical engine? Tell us the data rate and the parts of interest — we reply within one business day.