OSFP Optical Module Support ICs

Voltage conversion, power switching, comparator and logic ICs for 400G, 800G, and 1.6T OSFP transceivers.

OSFP (Octal Small Form-factor Pluggable) is the dominant pluggable optical module form factor for AI-cluster and hyperscale switch interconnect. Each module needs a small but precise set of support ICs that sit alongside the optical engine and DSP: multi-voltage conversion, hot-plug load switching, LPWn / RSTn signal decoding and signal level shifting. Magnias provides LDOs, buck converters, load switches, comparators, and logic for the support circuit, scaling cleanly from 400G to 1.6T module power budgets. The same BOM also supports Linear Pluggable Optics (LPO/LRO) variants, which remove the DSP and can cut module power by up to 40–50% depending on architecture. Only the core-supply current ratings change.

400G 800G 1.6T

OSFP optical transceiver module with fiber connector — OSFP pluggable optical module. Magnias supplies the LDO, buck, load switch, comparator, and buffer ICs that power and sequence the DSP and optical engine inside.

What an OSFP module needs from its support circuit

Each line below names a system-level need and the IC class that addresses it. The same set scales from 400G to 1.6T. Only the current ratings change.

System-level need	IC class that addresses it
Multi-voltage DC conversion	LDO + Buck
Low-IQ analog bias rails	Low-quiescent-current LDO
Sub-1 V efficient core supply	Buck (COT, 0.6 V ±1% FB)
Hot-plug inrush limiting	Load switch (controlled slew)
Independent rail sequencing	Two load switches
Output discharge on shutdown	Load switch with RPD
LPWn / RSTn decoding (OSFP MSA)	Dual comparator
Wire-OR interrupt drive	Open-drain buffer
Host CMOS to chipset signal bridge (CMIS 5.x two-wire management bus)	Auto-direction level translator (open-drain and push-pull)

Three circuit groups inside every OSFP module

The Magnias OSFP BOM splits into three functional groups. Each group has one or more positioned Magnias parts. Groups 1 and 2 are compared with a competitor benchmark further down.

Group 1

Voltage Conversion

Three Magnias parts cover the OSFP voltage tree: a fixed photodiode-bias LDO, a low-IQ analog bias LDO, and a high-efficiency buck for sub-1V core rails.

PR9030-2V5TF11 PSR9031-3V3TF11 MI2262G-F15

Group 2

Power Switching & Control Signals

Magnias load switches gate the 3.3V rails, a dual comparator decodes the host's LPWn and RSTn signals for the module MCU, and an open-drain buffer drives the wire-OR interrupt line.

PSW1510-A10 MVC1362-AC ML74LVC2G07-TW

Group 3

Voltage Domain Crossing

An auto-direction 2-bit level translator (two parts for four channels) moves the 3.3V host CMOS signals, including the CMIS 5.x two-wire management bus to the internal MCU, into the 1.8V chipset domain. Magnias MI2129B-F14 is rated 2 Mbps on open-drain lines such as I2C and 24 Mbps on push-pull lines.

MI2129B-F14

OSFP support-circuit block diagram

Choose a data rate to see the support circuit. The topology is shared across 400G / 800G / 1.6T; only the current ratings differ. Click (or tap) any blue block for the recommended Magnias part. Note: rail names (PD2V5, DVDDM1, 3V3_1, 3V3_2) are representative; actual labels vary by DSP / TIA / driver maker.

Block diagram

1.6T OSFP targets next-gen AI cluster interconnect. The support circuit keeps the same blocks with the highest current ratings: the buck's 2A rating on MI2262G-F15 and the load switch's 12A continuous rating on PSW1510-A10 are key headroom margins for this segment. Note: today's 1.6T pluggable OSFP modules (8 × 200G lanes, same cage as 800G) typically operate at ~20–25 W. OSFP-XD is a separate, non-backward-compatible 16-lane form factor that extends the thermal envelope up to ~30 W.

Tap any Magnias-coverage block (blue) to see the recommended part. Amber blocks are on the Magnias roadmap.

OSFP_VCC 3.3V

Host 3.3V input

T5V5 5.5V

Boosted analog rail

LDO· 2.5V Bias

PD2V5 bias rail

Analog Bias LDO

Analog bias rail

Synchronous Buck· 0.72V DSP Core

DVDDM1 core rail

Load Switch· 3V3_1

3V3_1 rail switch

Load Switch· 3V3_2

3V3_2 rail switch

Dual Comparator· LPWn / RSTn

LPWn / RSTn decode

Open-Drain Buffer· INT line

Wire-OR interrupt

Level Shifter

CMIS / I2C shift

DSP + Optical Engine

PAM4 DSP, optics

Host MCU + SIP

Module management

OSFP Edge Connector

Host edge connector

Magnias parts vs benchmark, side-by-side

Each row compares the Magnias-positioned part to a competitor benchmark on key parameters. The Magnias edge column highlights where the Magnias part wins.

Why Magnias Across the OSFP support BOM, Magnias targets three things: the lowest quiescent current on the analog rails, the smallest CSP / AQFN footprints on the load-switch and comparator stages, and 2× current headroom on the sub-1 V core buck.

Group 1· Voltage Conversion

Photodiode Bias LDO

PR9030-2V5TF11

Parameter	Magnias	Competitor
V_IN	2.5 – 6 V	1.4 – 5.5 V
V_OUT	2.5 V fixed	2.5 V fixed
I_OUT max	300 mA	150 mA
I_Q	500 nA	50 µA
Dropout	500 mV / 300 mA	230 mV / 150 mA
PSRR @ 1 kHz	60 dB	65 dB
Package	TDFN1010-4L	SON-6

Magnias edge 100× lower quiescent current, 2× output current, smaller package, comparable PSRR (within 5 dB of competitor at 1 kHz).

Analog Bias LDO (fixed 3.3 V)

PSR9031-3V3TF11

Parameter	Magnias	Competitor
V_IN	1.2 – 5.5 V	1.6 – 6.0 V
V_OUT	3.3 V fixed	4.0 V
I_OUT max	350 mA	300 mA
I_Q	1.3 µA	6.5 µA
PSRR @ 1 kHz	80 dB	95 dB

Magnias edge 5× lower quiescent current at the analog bias rail. Use the fixed PSR9031-3V3TF11 for 3.3 V rails; for custom analog voltages, use the adjustable PR9050-ADS5 (500 mA, 1.5 µA IQ, SOT23-5L).

Synchronous Buck

MI2262G-F15

Parameter	Magnias	Competitor
V_IN	2.55 – 6 V	≥ 3 V
V_OUT	0.6 – 6 V adjustable	0.72 V FB-set
V_REF	0.6 V ± 1%	≈ 0.5 V
I_OUT max	2 A	~1 A
f_SW	1.6 MHz	-
Efficiency	Up to 95%	-
Package	DFN1510-6L	WCSP

Magnias edge 2× output current. Sets the 0.72 V DSP core rail with an FB divider (new resistor values, different package).

Group 2· Power Switching & Control Signals

Hot-Plug Load Switch (12A class)

PSW1510-A10

Parameter	Magnias	Competitor
V_IN	0.1 – 5.5 V	0.5 – 13.5 V
I_OUT continuous	12 A	10.5 A
R_ON typ	3.2 mΩ (VBIAS 3.3 V) / 4 mΩ (VBIAS 5 V)	12.8 mΩ
Soft-start	Programmable slew	Fixed
Discharge	Integrated	Integrated
Package	AQFN1.5x2.0-10L	DFN-8 5 × 5 mm

Magnias edge 3.2× to 4× lower R_ON than the benchmark (3.2 to 4 mΩ vs 12.8 mΩ), meaningful at 12A continuous (less heat, more thermal margin). 88% smaller package footprint (3 mm² vs 25 mm²) frees board area for the optical engine. Programmable slew rate gives finer control of inrush than fixed-rate competitors. For lighter rails (< 3A) where AQFN is overkill, swap to PSW5192D-C11 (CSP1010-4L).

Dual Comparator (LPWn / RSTn)

MVC1362-AC

Parameter	Magnias	Competitor
Supply	1.2 – 5.5 V	1.6 – 6.5 V
Output	Push-pull	Push-pull
Channels	2 (dual)	2 (dual)
Input CM	Rail-to-rail	Rail-to-rail
t_pd	300 ns @ 100 mV	3 µs typ
Hysteresis	None (set externally)	Built-in
Package	AQFN1.5x1.5-8L	SC-70-8

Magnias edge 10× faster propagation and a smaller AQFN package. No internal reference or hysteresis: use an external reference or divider for the MSA thresholds.

Wire-OR Interrupt Buffer

ML74LVC2G07-TW

Parameter	Magnias	Competitor
V_CC	1.65 – 5.5 V	1.65 – 5.5 V
V_I tolerance	0 – 5.5 V	0 – 5.5 V
V_O off	0 – 5.5 V	0 – 5.5 V
I_OL drive	24 mA	24 mA
t_pd max	3.7 ns	~5 ns
Channels	2 (use 1)	1

Magnias edge Faster, dual-channel flexibility for future expansion.

Group 3· Voltage Domain Crossing

No side-by-side benchmark is shown for this group. Magnias MI2129B-F14 (DFN1410-8L) covers it: an auto-direction 2-bit translator rated 2 Mbps on open-drain CMIS / I2C lines and 24 Mbps on push-pull lines. Use 2 parts for 4 channels.

Magnias OSFP BOM summary

Function	Magnias P/N	Package	Applies to	Notes
Photodiode bias LDO	PR9030-2V5TF11	TDFN1010-4L	All rates· rail PD2V5	300 mA, 500 nA IQ. 100× lower IQ than competitor benchmark.
Analog Bias LDO (3.3 V fixed or ADJ)	PSR9031-3V3TF11	TDFN1010-4L	All rates· analog bias rails	350 mA, 1.3 µA IQ, 5× lower than competitor. PSR9031-3V3TF11 fixed for 3.3 V analog rails; PR9050-ADS5 adjustable (500 mA, 1.5 µA IQ) for custom analog voltages.
Synchronous Buck (DSP core)	MI2262G-F15	DFN1510-6L	All rates· DSP core rail DVDDM1	2 A, 1.6 MHz, up to 95% efficient. Sets 0.72V with an FB divider.
3V3 Hot-Plug Load Switch (main, 12A class)	PSW1510-A10	AQFN1.5x2.0-10L	All rates· two instances (3V3_1 / 3V3_2)	12 A continuous, R_ON typ 3.2 mΩ (VBIAS 3.3V) or 4 mΩ (VBIAS 5V). VIN 0.1–5.5V. Programmable slew rate + integrated discharge.
3V3 Hot-Plug Load Switch (alt)	PSW5192D-C11	CSP1010-4L	All rates· same position	3 A, R_ON 30 mΩ typ at VIN 3.6V, soft-start + auto-discharge (ROFF 250 Ω typ).
Dual Comparator (LPWn / RSTn decode)	MVC1362-AC	AQFN1.5x1.5-8L	All rates· LPWn / RSTn (OSFP MSA)	300 ns t_pd, push-pull, rail-to-rail inputs. 10× faster than competitor. No internal reference or hysteresis.
Open-Drain Buffer (wire-OR)	ML74LVC2G07-TW	SOT363	All rates· INT line (OSFP MSA)	Dual-channel, 24 mA I_OL, 5.5V tolerant. 3.7 ns t_pd max.
Level Shifter · 2-bit auto-direction × 2 parts	MI2129B-F14	DFN1410-8L	All rates · CMIS / I2C bus bridge to chipset	2 Mbps on open-drain CMIS / I2C lines, 24 Mbps push-pull. Use 2 parts for 4 channels covering the CMIS / I2C management bus from host CMOS into the chipset domain.

Request samples or an OSFP design review

Designing a 400G, 800G, or 1.6T OSFP module? Need samples of the LDO / buck / load-switch / comparator parts above, or want our FAE team to review the support-circuit BOM against your DSP and optical engine? Tell us the data rate and the parts of interest; we reply within one business day.